// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vpc_cvdr_reg_nmanager_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 14:37:49 Create file
// ******************************************************************************

#ifndef __VPC_CVDR_REG_NMANAGER_REG_OFFSET_H__
#define __VPC_CVDR_REG_NMANAGER_REG_OFFSET_H__

/* VPC_CVDR_REG_NMANAGER Base address of Module's Register */
#define SOC_VPC_CVDR_REG_NMANAGER_BASE                       (0x10000)

/******************************************************************************/
/*                      SOC VPC_CVDR_REG_NMANAGER Registers' Definitions                            */
/******************************************************************************/

#define SOC_VPC_CVDR_REG_NMANAGER_VPC_CVDR_CFG_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x0)    /* CVDR config register. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_CVDR_DEBUG_EN_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x4)    /* CVDR debug register enable. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_CVDR_DEBUG_REG       (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x8)    /* CVDR debug register. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_CVDR_WR_QOS_CFG_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xC)    /* AXI Write QOS/Pressure configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_CVDR_RD_QOS_CFG_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x10)   /* AXI Read QOS/Pressure configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_FORCE_CLK_REG        (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x14)   /* Force clock ON */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_OTHER_RO_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x20)   /* Spare Other RO. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_OTHER_RW_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x24)   /* Spare Other RW. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_CFG_0_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x30)   /* Video port write Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_FS_0_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x34)   /* AXI address Frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_LINE_0_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x38)   /* AXI line wrap and line stride. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_IF_CFG_0_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x3C)   /* Video port write interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_CFG_1_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x40)   /* Video port write Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_FS_1_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x44)   /* AXI address Frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_LINE_1_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x48)   /* AXI line wrap and line stride. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_IF_CFG_1_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x4C)   /* Video port write interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_CFG_2_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x50)   /* Video port write Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_FS_2_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x54)   /* AXI address Frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_LINE_2_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x58)   /* AXI line wrap and line stride. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_IF_CFG_2_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x5C)   /* Video port write interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_CFG_3_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x60)   /* Video port write Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_FS_3_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x64)   /* AXI address Frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_LINE_3_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x68)   /* AXI line wrap and line stride. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_IF_CFG_3_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x6C)   /* Video port write interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_CFG_4_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x70)   /* Video port write Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_FS_4_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x74)   /* AXI address Frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_AXI_LINE_4_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x78)   /* AXI line wrap and line stride. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_IF_CFG_4_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x7C)   /* Video port write interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_WR_0_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x830)  /* Video port write Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_WR_1_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x834)  /* Video port write Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_WR_2_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x838)  /* Video port write Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_WR_3_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x83C)  /* Video port write Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_WR_4_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x840)  /* Video port write Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_CFG_0_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA30)  /* Video port read Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_LWG_0_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA34)  /* Line width generation. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_FHG_0_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA38)  /* Frame height generation. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_AXI_FS_0_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA3C)  /* AXI frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_AXI_LINE_0_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA40)  /* Line Wrap definition. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_IF_CFG_0_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA44)  /* Video port read interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_DEBUG_0_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA4C)  /* Video Port Read DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_CFG_1_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA50)  /* Video port read Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_LWG_1_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA54)  /* Line width generation. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_FHG_1_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA58)  /* Frame height generation. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_AXI_FS_1_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA5C)  /* AXI frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_AXI_LINE_1_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA60)  /* Line Wrap definition. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_IF_CFG_1_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA64)  /* Video port read interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_DEBUG_1_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA6C)  /* Video Port Read DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_CFG_2_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA70)  /* Video port read Configuration. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_LWG_2_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA74)  /* Line width generation. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_FHG_2_REG      (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA78)  /* Frame height generation. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_AXI_FS_2_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA7C)  /* AXI frame start. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_AXI_LINE_2_REG (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA80)  /* Line Wrap definition. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_IF_CFG_2_REG   (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA84)  /* Video port read interface configuration: prefetch or reset or stall capability. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_RD_DEBUG_2_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0xA8C)  /* Video Port Read DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_RD_0_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1230) /* Video port read Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_RD_1_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1234) /* Video port read Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_LIMITER_VP_RD_2_REG  (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1238) /* Video port read Access limiter. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_SPARE_0_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D30) /* Spare. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_SPARE_1_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D34) /* Spare. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_SPARE_2_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D38) /* Spare. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_SPARE_3_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D3C) /* Spare. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_DEBUG_0_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D40) /* Video Port Write DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_DEBUG_1_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D44) /* Video Port Write DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_DEBUG_2_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D48) /* Video Port Write DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_DEBUG_3_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D4C) /* Video Port Write DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_VP_WR_DEBUG_4_REG    (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1D50) /* Video Port Write DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_0_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F40) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_1_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F44) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_2_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F48) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_3_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F4C) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_4_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F50) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_5_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F54) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_6_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F58) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_7_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F5C) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_8_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F60) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_9_REG          (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F64) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_10_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F68) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_11_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F6C) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_12_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F70) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_13_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F74) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_14_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F78) /* DEBUG information. */
#define SOC_VPC_CVDR_REG_NMANAGER_VPC_DEBUG_15_REG         (SOC_VPC_CVDR_REG_NMANAGER_BASE + 0x1F7C) /* DEBUG information. */

#endif // __VPC_CVDR_REG_NMANAGER_REG_OFFSET_H__
